The present invention relates to a graphics memory system and, more particularly, to a graphics memory system that utilizes detached Z buffering in conjunction with a batching architecture to read and write Z data and pixel data in batches, thereby reducing paging overhead.
Many high performance graphics memory systems xe2x80x9cattachxe2x80x9d the memory for the Z coordinate, commonly referred to as the Z buffer, to the memory for the pixel color, commonly referred to as the image buffer, so that the Z coordinate and the color values for the pixel can reside in the same memory page, i.e., the same row address, of the frame buffer memory of the graphics memory system. In these types of systems, a pixel is processed by reading the old Z coordinate for the pixel from the Z buffer, comparing the old Z coordinate with a new Z coordinate, and, if the new Z coordinate passes the Z comparison test, writing the new Z coordinate and the associated pixel color into the Z buffer and image buffer, respectively, of the frame buffer memory. Once these steps have been performed, the next pixel is processed in an identical manner.
The Z comparison test is performed to determine whether the new pixel (i.e., the Z coordinate and color) is in front of the old pixel on the screen and needs to be written into the frame buffer memory or whether it can be discarded. If the Z coordinate associated with an X,Y screen coordinate is behind the Z coordinate contained in the Z buffer memory that is associated with that same screen coordinate, the new pixel can be discarded because the new pixel would not be viewable on the display monitor even if it was displayed. This situation corresponds to a Z comparison failure.
Since the Z coordinate and the color for a particular pixel are stored in the same page in the frame buffer memory, attachment of the Z coordinate to the pixel color eliminates the need for xe2x80x9cre-pagingxe2x80x9d, i.e., closing the current page of memory and opening a new page of memory when switching between Z coordinate accesses and color accesses. However, attachment of the Z coordinate to the color produces an undesirable side effect as well, namely, it reduces the size of a page in XY screen coordinates. A page of synchronous graphics RAM (SGRAM) memory may store, for example, 1024 bytes. If this page is shared for 16-bit pixel color and Z coordinate values, then only 512 bytes are available to be used for the colors while the other 512 bytes must be used for the Z coordinates. Thus, the shape of the page in two-dimensional screen coordinate space might be 32xc3x978 pixels, whereas if the memory for Z coordinates were detached and moved into a different page, the shape of the page in accordance with this example, could be 32xc3x9716 pixels. The taller page would be advantageous for both vectors and triangles.
Another undesirable side effect caused by attaching the Z memory to the pixel color memory so that each pixel can be processed to completion before processing begins on the next pixel, is that bus inefficiencies result. Specifically, processing a pixel to completion before beginning processing on the next pixel wastes bus bandwidth because each time the memory bus is xe2x80x9cturned aroundxe2x80x9d, i.e., changed from reads to writes or from writes to reads, dead states must be utilized to avoid bus contention problems and to satisfy pipe latencies.
Graphics operating systems for personal computers (PCs) usually allocate Z buffer memory independently from allocations for image buffer memory. Therefore, for PC graphics operating systems, it is preferable to utilize a graphics memory architecture that detaches the Z buffer from their associated image buffer to provide independent allocation for this memory. However, as stated above, detachment of the Z buffer from the image buffer requires that the frame buffer memory be re-paged each time accesses to the frame buffer memory are switched between Z coordinate accesses and color accesses, which can eliminate advantages attributable to the resulting larger page size.
Accordingly, a need exists for a graphics memory system that utilizes detached Z buffering to obtain the advantages thereof while eliminating the inefficiencies associated with re-paging when switching between a Z access and the associated color access for each pixel.
The present invention provides a graphics memory system of a computer graphics display system which utilizes a batching architecture in conjunction with detached Z buffering for minimizing paging overhead. The graphics memory system comprises a memory controller which receives a batch of pixels from a host CPU of the computer graphics display system when a 3D rendering mode is in effect. Each pixel comprises a pixel color and corresponding Z coordinate data. The memory controller then performs a Z comparison test wherein Z coordinate data of the batch is compared with existing Z coordinate data stored in a frame buffer memory to determine whether or not each new pixel of the batch associated with the Z coordinate being compared should be written into the frame buffer memory. If the results of a Z comparison test pass, the new pixel color and Z coordinate data are queued for writing into the frame buffer memory.
In accordance with the preferred embodiment of the present invention, two memory controllers are implemented in the graphics memory system, each accessing its own frame buffer memory, which is comprised of a RAM storage device. Each of the frame buffer memory elements comprises an image buffer region and a Z buffer region. The image buffer region is separate from the Z buffer region. Z coordinate data are stored in the Z buffer region and pixel colors are stored in the image buffer region. Therefore, the Z coordinate data is xe2x80x9cdetachedxe2x80x9d from the pixel colors.
Each of the memory controllers preferably comprises a Write Z FIFO, a Read Z FIFO, a Write Pixel FIFO, and a RAM controller. These FIFOs are chosen to have a size which is appropriate for the batch size being utilized The memory controllers preferably are identical in nature. The Z coordinate data received by the memory controller from its respective frame buffer memory element are read out of addresses of the frame buffer memory element which correspond to addresses stored by the RAM controller in the Z Read FIFO. If the Z comparison passes, the new Z coordinate data is written into the Write Z FIFO and the corresponding pixel colors are written into the Write Pixel FIFO. The Z coordinate data written into the Write Z FIFO are stored by the RAM controller at addresses corresponding to the addresses stored in the Z Read FIFO. The pixel colors written into the Write Pixel FIFO are stored by the RAM controller at their associated row and column addresses in the frame buffer memory.
In accordance with the preferred embodiment of the present invention, the results of the Z comparison test for a batch are provided to both of the memory controllers. The results of the Z comparison tests are preferably stored in a Z Compare Results FIFO. Each pixel color has an identification tag associated with it and each Z comparison test result has an identification tag associated with it. The memory controllers determine whether an identification tag of a pixel color matches an identification tag of a Z comparison test result. When a match occurs, the memory controller analyzes the Z comparison result to determine whether the pixel color associated with the matching identification tag should be saved in the frame buffer memory. Whenever a match is found, an acknowledgment is provided to the Z Compare Result FIFO which causes the corresponding compare result to be unloaded from the Z Compare Result FIFO.
Other features and advantages of the present invention will become apparent from the following discussion, drawings and claims.